9 search results - page 1 / 2 » An ACL2 Proof of Write Invalidate Cache Coherence |
CAV
1998
Springer
13 years 9 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
ICPP
1990
IEEE
13 years 9 months ago
1990
IEEE
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
This paper explores a new technique called coherence decoupling, which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol ...
CODES
2009
IEEE
13 years 9 months ago
2009
IEEE
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
CAL
2010
13 years 1 months ago
2010
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...