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» An Automatic Test Pattern Generator for Large Sequential Cir...
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VTS
1998
IEEE
97views Hardware» more  VTS 1998»
13 years 10 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
13 years 10 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 10 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
COR
2008
164views more  COR 2008»
13 years 5 months ago
Observations in using parallel and sequential evolutionary algorithms for automatic software testing
In this paper we analyze the application of parallel and sequential evolutionary algorithms (EAs) to the automatic test data generation problem. The problem consists of automatica...
Enrique Alba, J. Francisco Chicano
FPL
2004
Springer
94views Hardware» more  FPL 2004»
13 years 11 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...