Sciweavers

10 search results - page 1 / 2
» An Embedded Core DFT Scheme to Obtain Highly Compressed Test...
Sort
View
ATS
1999
IEEE
99views Hardware» more  ATS 1999»
13 years 9 months ago
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
Abhijit Jas, Kartik Mohanram, Nur A. Touba
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
13 years 6 months ago
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...
V. Tenentes, Xrysovalantis Kavousianos, Emmanouil ...
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
13 years 10 months ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
13 years 10 months ago
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
Anshuman Chandra, Krishnendu Chakrabarty