13 search results - page 2 / 3 » An Enhancement for a Scheduling Logic Pipelined over two Cyc... |
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
CAINE
2003
13 years 6 months ago
2003
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
CF
2005
ACM
13 years 7 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
TPDS
2010
13 years 3 months ago
2010
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...