Sciweavers

177 search results - page 2 / 36
» An Interconnect Energy Model Considering Coupling Effects
Sort
View
ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
TVLSI
2002
144views more  TVLSI 2002»
13 years 5 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail
DELTA
2008
IEEE
13 years 12 months ago
Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs
Analytical compact form models for the signal transient and crosstalk noise of two-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and ...
Taehoon Kim, Dongchul Kim, Jung-A Lee, Yungseon Eo
DAC
2000
ACM
14 years 6 months ago
On switch factor based analysis of coupled RC interconnects
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
13 years 11 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...