60 search results - page 1 / 12 » An Issue Logic for Superscalar Microprocessors |
CAINE
2003
13 years 6 months ago
2003
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
DSD
2002
IEEE
13 years 9 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
CF
2005
ACM
13 years 6 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
Burch and Dill [3] described an automatic method for verifying a pipelined processor against its instruction setarchitecture(ISA). We describethree techniquesfor improving this me...