203 search results - page 1 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...