24 search results - page 1 / 5 » An area-optimality study of floorplanning |
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Abstract-- In this paper we present the first bus-aware microarchitectural floorplanning. Our goal is to study the impact of bus routability on other important floorplanning object...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer inserti...