24 search results - page 4 / 5 » An area-optimality study of floorplanning |
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] te...
ICMCS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper studied an H.264 HDTV decoder on two multiprocessor system-on-chip architectures. Two types of networks-on-chip, the RAW network and the applicationspecific networks-on...
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
ISPD
2012
ACM
12 years 1 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...