40 search results - page 1 / 8 » An automated design flow for 3D microarchitecture evaluation |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
ICRA
2000
IEEE
13 years 9 months ago
2000
IEEE
A tele-operated system in a robot greatly reduces the demands on the human operator, although some human intervention is still required to perform such tasks as insulator recognit...