10 search results - page 1 / 2 » An automated methodology for memory-conscious mapping of DSP... |
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
A high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse grain components that their flex...
ASAP
2005
IEEE
13 years 10 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...
ESTIMEDIA
2007
Springer
13 years 8 months ago
2007
Springer
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...