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TCAD
2008
114views more  TCAD 2008»
13 years 5 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
DSD
2006
IEEE
93views Hardware» more  DSD 2006»
13 years 11 months ago
High-Level Decision Diagram based Fault Models for Targeting FSMs
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
Jaan Raik, Raimund Ubar, Taavi Viilukas
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 10 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
INFSOF
2007
104views more  INFSOF 2007»
13 years 5 months ago
A state-based approach to integration testing based on UML models
: Correct functioning of object-oriented software depends upon the successful integration of classes. While individual classes may function correctly, several new faults can arise ...
Shaukat Ali, Lionel C. Briand, Muhammad Jaffar-Ur ...
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 10 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz