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ISLPED
2000
ACM
80views Hardware» more  ISLPED 2000»
13 years 9 months ago
An improved pass transistor synthesis method for low power, high speed CMOS circuits
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Tudor Vinereanu, Sverre Lidholm
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
13 years 11 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 5 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
TVLSI
2008
106views more  TVLSI 2008»
13 years 4 months ago
New Non-Volatile Memory Structures for FPGA Architectures
A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
David Choi, Kyu Choi, John D. Villasenor