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ITC
1996
IEEE
96views Hardware» more  ITC 1996»
13 years 9 months ago
Analysis and Detection of Timing Failures in an Experimental Test Chip
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin...
VTS
1996
IEEE
114views Hardware» more  VTS 1996»
13 years 9 months ago
Quantitative analysis of very-low-voltage testing
Some weak static CMOS chips can be detected by testing them with a very low supply voltage -- between 2 and 2.5 times the threshold voltage Vt of the transistors. A weak chip is o...
Jonathan T.-Y. Chang, Edward J. McCluskey
ITC
2000
IEEE
93views Hardware» more  ITC 2000»
13 years 9 months ago
Stuck-fault tests vs. actual defects
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and comp...
Edward J. McCluskey, Chao-Wen Tseng
MR
2002
100views Robotics» more  MR 2002»
13 years 4 months ago
No-flow underfill flip chip assembly--an experimental and modeling analysis
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken b...
Hua Lu 0003, K. C. Hung, Stoyan Stoyanov, Chris Ba...
ETS
2011
IEEE
230views Hardware» more  ETS 2011»
12 years 4 months ago
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak,...