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IPPS
2006
IEEE
14 years 5 days ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
14 years 13 days ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
SIGMETRICS
2008
ACM
150views Hardware» more  SIGMETRICS 2008»
13 years 6 months ago
Performance of random medium access control, an asymptotic approach
Random Medium-Access-Control (MAC) algorithms have played an increasingly important role in the development of wired and wireless Local Area Networks (LANs) and yet the performanc...
Charles Bordenave, David McDonald, Alexandre Prout...
ISCAS
2006
IEEE
104views Hardware» more  ISCAS 2006»
14 years 5 days ago
Average lengths of wire routing under M-architecture and X-architecture
— The X-architecture is a new integrated-circuit wiring technique in the physical design. Compared with the currently used M-architecture, which uses either horizontal or vertica...
S. P. Shang, Xiaodong Hu, Tong Jing
ASPLOS
2008
ACM
13 years 8 months ago
No "power" struggles: coordinated multi-level power management for the data center
Power delivery, electricity consumption, and heat management are becoming key challenges in data center environments. Several past solutions have individually evaluated different ...
Ramya Raghavendra, Parthasarathy Ranganathan, Vani...