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ISCAS
2006
IEEE
116views Hardware» more  ISCAS 2006»
13 years 11 months ago
Signal processing for brain-computer interface: enhance feature extraction and classification
Abstract-In this paper we present a new scheme for brain imaginary movement invovles sophisticated spatial-temporalsignal processing and classification for electroencephalogram spe...
Haihong Zhang, Cuntai Guan, Yuanqing Li
SENSYS
2009
ACM
14 years 1 hour ago
Run time assurance of application-level requirements in wireless sensor networks
Continuous and reliable operation of WSNs is notoriously difficult to guarantee due to hardware degradation and environmental changes. In this paper, we propose and demonstrate a ...
Jingyuan Li, Yafeng Wu, Krasimira Kapitanova, John...
CODES
2005
IEEE
13 years 10 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
SAMOS
2004
Springer
13 years 10 months ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
CODES
2009
IEEE
13 years 10 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...