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    MJ
    2006
    145views more  MJ 2006»
    A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
    13 years 5 months ago
    A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
    Download  www.vlsi.ee.upatras.gr
    In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
    Michalis D. Galanis, Athanasios Milidonis, Athanas...
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    DAC
    2000
    ACM
    129views Computer Architecture» more  DAC 2000»
    System design of active basestations based on dynamically reconfigurable hardware
    13 years 10 months ago
    System design of active basestations based on dynamically reconfigurable hardware
    Download  nesl.ee.ucla.edu
    – This paper describes the system design and implementation of Active Basestations, a novel application of the run-time reconfigurable hardware technology whose applications have...
    Athanassios Boulis, Mani B. Srivastava
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    FCCM
    2009
    IEEE
    106views VLSI» more  FCCM 2009»
    Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
    13 years 9 months ago
    Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
    Download  www.comp.nus.edu.sg
    Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
    Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
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    DAC
    2003
    ACM
    153views Computer Architecture» more  DAC 2003»
    Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
    14 years 6 months ago
    Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
    Download  www.ivgroup.ee.ucla.edu
    This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...
    David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazu...
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    FPGA
    2007
    ACM
    124views FPGA» more  FPGA 2007»
    Efficient hardware checkpointing: concepts, overhead analysis, and implementation
    13 years 9 months ago
    Efficient hardware checkpointing: concepts, overhead analysis, and implementation
    Download  www12.informatik.uni-erlangen.de
    Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
    Dirk Koch, Christian Haubelt, Jürgen Teich
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