9 search results - page 1 / 2 » Analytical minimization of half-perimeter wirelength |
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Inspired by recent success of analytical placers that use a logarithmsum-exponential (LSE) to smooth half-perimeter wirelength (HPWL), we consider in this paper two alternative sm...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
ISPD
2005
ACM
13 years 10 months ago
2005
ACM
Automatic circuit placement has received renewed interest recently given the rapid increase of circuit complexity, increase of interconnect delay, and potential sub-optimality of ...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by V...