11 search results - page 1 / 3 » Analytical models for leakage power estimation of memory arr... |
CODES
2004
IEEE
13 years 8 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...