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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
8 years 11 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
DAC
2009
ACM
9 years 5 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
CASES
2007
ACM
8 years 8 months ago
SCCP/x: a compilation profile to support testing and verification of optimized code
Embedded systems are often used in safety-critical environments. Thus, thorough testing of them is mandatory. A quite active research area is the automatic test-case generation fo...
Raimund Kirner
TSE
1998
131views more  TSE 1998»
8 years 4 months ago
Experiences Using Lightweight Formal Methods for Requirements Modeling
—This paper describes three case studies in the lightweight application of formal methods to requirements modeling for spacecraft fault protection systems. The case studies diffe...
Steve M. Easterbrook, Robyn R. Lutz, Richard Covin...
STVR
2010
80views more  STVR 2010»
7 years 11 months ago
Testing coupling relationships in object-oriented programs
As we move to developing object-oriented programs, the complexity traditionally found in functions and procedures is moving to the connections among components. Different faults o...
Roger T. Alexander, Jeff Offutt, Andreas Stefik
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