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DATE
2008
IEEE
163views Hardware» more  DATE 2008»
13 years 12 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 5 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
ANCS
2006
ACM
13 years 11 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
DAC
2007
ACM
14 years 6 months ago
Computationally Efficient Power Integrity Simulation for System-on-Package Applications
Power integrity simulation for system-on-package (SoP) based modules is a crucial bottleneck in the SoP design flow. In this paper, the multi-layer finite difference method (M-FDM...
Krishna Bharath, Ege Engin, Madhavan Swaminathan, ...
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan