Sciweavers

14 search results - page 1 / 3
» Approximate logic circuits for low overhead, non-intrusive c...
Sort
View
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
13 years 11 months ago
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error dete...
Mihir R. Choudhury, Kartik Mohanram
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
13 years 11 months ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
DSD
2006
IEEE
113views Hardware» more  DSD 2006»
13 years 6 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
ISQED
2003
IEEE
134views Hardware» more  ISQED 2003»
13 years 10 months ago
Concurrent Fault Detection in Random Combinational Logic
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circui...
Petros Drineas, Yiorgos Makris
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
13 years 10 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba