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» Architectural Support for Runtime 2D Partial Reconfiguration
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ERSA
2006
114views Hardware» more  ERSA 2006»
13 years 6 months ago
Architectural Support for Runtime 2D Partial Reconfiguration
: Traditional FPGA architectures can potentially allow the dynamic swap in and out of hardware tasks through 2D partial reconfiguration. A segmented bus structure is proposed to be...
Fei Wang, Jack S. N. Jean
DAGSTUHL
2006
13 years 6 months ago
Physical 2D Morphware and Power Reduction Methods for Everyone
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
Jürgen Becker, Michael Hübner, Katarina ...
DAC
2002
ACM
14 years 5 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
IEE
1998
90views more  IEE 1998»
13 years 4 months ago
On the role of software architectures in runtime system reconfiguration
Society’s increasing dependence on software-intensive systems is driving the need for dependable, robust, continuously available systems. Runtime system reconfiguration is one a...
Peyman Oreizy, Richard N. Taylor
FPL
2009
Springer
145views Hardware» more  FPL 2009»
13 years 9 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...