125 search results - page 2 / 25 » Area and delay trade-offs in the circuit and architecture de... |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
FPGA
2000
ACM
13 years 9 months ago
2000
ACM
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
ISCA
1994
IEEE
13 years 9 months ago
1994
IEEE
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...