3 search results - page 1 / 1 » Area efficient loop filter design for charge pump phase lock... |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CS...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...