12 search results - page 3 / 3 » Area fill synthesis for uniform layout density |
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...