8 search results - page 1 / 2 » Area optimization for leakage reduction and thermal stabilit... |
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
TVLSI
2008
13 years 4 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...