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» Area-Efficient Area Pad Design for High Pin-Count Chips
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GLVLSI
1999
IEEE
105views VLSI» more  GLVLSI 1999»
10 years 4 days ago
Area-Efficient Area Pad Design for High Pin-Count Chips
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...
Louis Luh, John Choma Jr., Jeffrey T. Draper
DAC
1998
ACM
10 years 8 months ago
Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
Jaewon Oh, Massoud Pedram
ICCAD
2008
IEEE
130views Hardware» more  ICCAD 2008»
10 years 2 months ago
Area-I/O flip-chip routing for chip-package co-design
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
Jia-Wei Fang, Yao-Wen Chang
ASPDAC
2008
ACM
145views Hardware» more  ASPDAC 2008»
9 years 9 months ago
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
Minje Jun, Sungjoo Yoo, Eui-Young Chung
DAC
2006
ACM
10 years 8 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
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