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GLVLSI
1999
IEEE

Area-Efficient Area Pad Design for High Pin-Count Chips

9 years 11 months ago
Area-Efficient Area Pad Design for High Pin-Count Chips
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top metal layer and therefore allow active circuitry to be laid out underneath. With identical functional elements grouped together, a group of pad drivers share the same well and can be placed tightly together. The use of silicided di usion reduces the well contact to di usion contact spacing requirement. By taking advantage of this spacing requirement and using serpentine gate layout, a driver's size can be e ectively reduced without reducing the driving capacity. An embedded multicomputer router interface chip has been implemented using these techniques and has achieved 554 pads in a 9mm 6mm chip with a 0.8m single-poly 3-metal N-well CMOS process.
Louis Luh, John Choma Jr., Jeffrey T. Draper
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where GLVLSI
Authors Louis Luh, John Choma Jr., Jeffrey T. Draper
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