5 search results - page 1 / 1 » Area-Efficient Area Pad Design for High Pin-Count Chips |
GLVLSI
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...
DAC
1998
ACM
14 years 5 months ago
1998
ACM
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
ICCAD
2008
IEEE
13 years 11 months ago
2008
IEEE
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...