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DATE
2009
IEEE
163views Hardware» more  DATE 2009»
13 years 9 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
CSSE
2002
IEEE
13 years 5 months ago
A fault tolerant access to legacy database systems using CORBA technology
This work presents a software-implemented fault tolerance approach for building a reliable database application in a CORBA environment. Database applications have functional requi...
Domenico Cotroneo, Nicola Mazzocca, Luigi Romano, ...
CGO
2005
IEEE
13 years 11 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
STORAGESS
2005
ACM
13 years 10 months ago
An approach for fault tolerant and secure data storage in collaborative work environments
We describe a novel approach for building a secure and fault tolerant data storage service in collaborative work environments, which uses perfect secret sharing schemes to store d...
Arun Subbiah, Douglas M. Blough
DSN
2007
IEEE
13 years 11 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...