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» Asynchronous Architectures for Nanometer Scales
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DAC
2007
ACM
14 years 6 months ago
Nanometer Device Scaling in Subthreshold Circuits
Scott Hanson, Mingoo Seok, Dennis Sylvester, David...
HPCA
2005
IEEE
13 years 11 months ago
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
Krishnan Sundaresan, Nihar R. Mahapatra
DAC
2001
ACM
14 years 6 months ago
Future Performance Challenges in Nanometer Design
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
Dennis Sylvester, Himanshu Kaul
DATE
2008
IEEE
144views Hardware» more  DATE 2008»
13 years 11 months ago
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces
The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bioelectronic interfaces is raising a number of important issues concerning circuit arc...
Carlotta Guiducci, Alexandre Schmid, Frank K. G&uu...