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FDL
2008
IEEE
13 years 6 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
ICCL
1992
IEEE
13 years 9 months ago
An automatically generated and provably correct compiler for a subset of Ada
We describe the automatic generation of a provably correct compiler for a non-trivial subset of Ada. The compiler is generated from an emantic description; it emits absolute code ...
Jens Palsberg
DAC
1997
ACM
13 years 9 months ago
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy...
DATE
2004
IEEE
181views Hardware» more  DATE 2004»
13 years 8 months ago
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based...
Manuel Hohenauer, Hanno Scharwächter, Kingshu...
FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
13 years 8 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose