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» Automatic FIR Filter Generation for FPGAs
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SAMOS
2005
Springer
12 years 8 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) ļ¬lters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
12 years 8 months ago
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems
The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and h...
Dimitrios Soudris, K. Sgouropoulos, Konstantinos T...
FPL
2008
Springer
254views Hardware» more  FPL 2008»
12 years 4 months ago
Digital hilbert transformers for FPGA-based phase-locked loops
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
Martin Kumm, M. Shahab Sanjari
FPL
2008
Springer
110views Hardware» more  FPL 2008»
12 years 4 months ago
Automatic generation of run-time parameterizable configurations
In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (Field Programmable Gate Arrays) can ...
Karel Bruneel, Dirk Stroobandt
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
12 years 7 months ago
Automatically mapping applications to a self-reconfiguring platform
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...
Karel Bruneel, Fatma Abouelella, Dirk Stroobandt
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