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DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 10 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
SAMOS
2010
Springer
13 years 4 months ago
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators
Abstract—Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to en...
Jens Huthmann, Peter Muller, Florian Stock, Dietma...
DDECS
2007
IEEE
133views Hardware» more  DDECS 2007»
13 years 7 months ago
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties
— From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the sig...
Yann Oddos, Katell Morin-Allory, Dominique Borrion...
TCAD
2010
102views more  TCAD 2010»
13 years 14 days ago
Functional Test Generation Using Efficient Property Clustering and Learning Techniques
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
Mingsong Chen, Prabhat Mishra
DAC
2004
ACM
14 years 6 months ago
Automatic generation of breakpoint hardware for silicon debug
Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpo...
Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep...