15 search results - page 2 / 3 » Automatic SystemC TLM generation for custom communication pl... |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
LCTRTS
2010
Springer
13 years 12 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
In order for collective communication routines to achieve high performance on different platforms, they must be able to adapt to the system architecture and use different algori...
FDL
2004
IEEE
13 years 8 months ago
2004
IEEE
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...