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» Automatic Verification of Pipelined Microprocessors
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DATE
2004
IEEE
174views Hardware» more  DATE 2004»
13 years 8 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt
TODAES
1998
68views more  TODAES 1998»
13 years 4 months ago
Specification and verification of pipelining in the ARM2 RISC microprocessor
Abstract State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a ...
James K. Huggins, David Van Campenhout
ACSD
1998
IEEE
90views Hardware» more  ACSD 1998»
13 years 9 months ago
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
Miroslav N. Velev, Randal E. Bryant
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
13 years 10 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...