51 search results - page 2 / 11 » Automatic Verification of Sequential Circuit Designs |
TCAD
2002
13 years 4 months ago
2002
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
CAV
2010
Springer
13 years 5 months ago
2010
Springer
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transforma...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...