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FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 9 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
VLSID
2004
IEEE
138views VLSI» more  VLSID 2004»
14 years 5 months ago
Synthesis-driven Exploration of Pipelined Embedded Processors
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 5 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 9 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
DAC
2003
ACM
14 years 6 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...