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DATE
2007
IEEE
142views Hardware» more  DATE 2007»
13 years 11 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 11 months ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A 52mW 1200MIPS compact DSP for multi-core media SoC
- This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-c...
Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting ...
DAC
2008
ACM
14 years 6 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
AMOST
2005
ACM
13 years 10 months ago
Test prioritization for pairwise interaction coverage
Interaction testing is widely used in screening for faults. In software testing, it provides a natural mechanism for testing systems to be deployed on a variety of hardware and so...
Renée C. Bryce, Charles J. Colbourn