47 search results - page 9 / 10 » Bandwidth-Constrained Mapping of Cores onto NoC Architecture... |
VLSID
2010
IEEE
13 years 9 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
ICASSP
2010
IEEE
13 years 5 months ago
2010
IEEE
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...
ISLPED
2000
ACM
13 years 9 months ago
2000
ACM
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
ISVLSI
2005
IEEE
13 years 11 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...