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ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 8 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 5 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
FPL
2004
Springer
112views Hardware» more  FPL 2004»
13 years 10 months ago
Storage Allocation for Diverse FPGA Memory Specifications
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
Dalia Dagher, Iyad Ouaiss
DAGSTUHL
2004
13 years 6 months ago
Removing Cycles in Esterel Programs
Abstract. Synchronous programs may contain cyclic signal interdependencies. This prohibits a static scheduling, which limits the choice of available compilation techniques for such...
Jan Lukoschus, Reinhard von Hanxleden