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» Bit-Width Selection for Data-Path Implementations
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ISSS
1999
IEEE
157views Hardware» more  ISSS 1999»
12 years 4 months ago
Bit-Width Selection for Data-Path Implementations
Specifications of data computations may not necessarily describe the ranges of the intermediate results that can be generated. However, such information is critical to determine t...
Carlos Carreras, Juan A. López, Octavio Nie...
FCCM
2004
IEEE
109views VLSI» more  FCCM 2004»
12 years 3 months ago
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation...
Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter...
FPL
2010
Springer
168views Hardware» more  FPL 2010»
11 years 9 months ago
Pipelined FPGA Adders
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. Thi...
Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasc...
CODES
2005
IEEE
12 years 5 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
12 years 3 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...
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