Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor

Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP1, the first prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 outperformed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance. 1 DRP Overview DRP is a coarse-grain reconfigurable processor core which can be integrated into ASICs and SOCs. The primitive unit of DRP Core is called a `Tile', and DRP Core consists of arbitrary number of Tiles. The number of Tiles can be expandable, horizontally and ve...

• Type: Conference
• Year: 2004
• Where: FCCM
• Authors: Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
• Keywords: DRP Core, FCCM 2004, Reconfigurable Processor, Single Drp Chip, VLSI