9 search results - page 1 / 2 » Block-based Static Timing Analysis with Uncertainty |
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
JPDC
2008
13 years 5 months ago
2008
This research investigates the problem of robust static resource allocation for distributed computing systems operating under imposed Quality of Service (QoS) constraints. Often, ...