5 search results - page 1 / 1 » Blockage-avoiding buffered clock-tree synthesis for clock la... |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...
DAC
2006
ACM
13 years 10 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...