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ASPDAC
2008
ACM

Clock tree synthesis with data-path sensitivity matching

10 years 1 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization disregard clock tree variation, we consider both. Using both clock and data-path variations together, we present a novel sensitivitymatching algorithm that allows clock tree skews to be intentionally correlated with data-path sensitivities to ameliorate timing violations due to variation. Our statistical tuning shows an improvement in terms of expected clock skew and clock skew variation over previously published robust algorithms.
Matthew R. Guthaus, Dennis Sylvester, Richard B. B
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where ASPDAC
Authors Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
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