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» Buffer Insertion for Noise and Delay Optimization
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ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
Weiping Shi, Zhuo Li, Charles J. Alpert
ICCAD
1995
IEEE
79views Hardware» more  ICCAD 1995»
13 years 8 months ago
Optimal wire sizing and buffer insertion for low power and a generalized delay model
John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
DAC
1999
ACM
13 years 9 months ago
Buffer Insertion with Accurate Gate and Interconnect Delay Computation
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
ICCAD
2004
IEEE
145views Hardware» more  ICCAD 2004»
14 years 2 months ago
Accurate estimation of global buffer delay within a floorplan
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 5 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong