5 search results - page 1 / 1 » Buffer design and optimization for lut-based structured ASIC... |
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
DAC
2004
ACM
13 years 8 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...