6 search results - page 1 / 2 » Buffered clock tree sizing for skew minimization under power... |
ASPDAC
2010
ACM
13 years 2 months ago
2010
ACM
DAC
2006
ACM
13 years 10 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...